The prior art measures a current created by an applied voltage to measure gate length and drain/source gate overlap for MOSFET's.
As the miniaturization of MOS devices continues accurate production measurements of gate length and drain/source gate overlap become more important. The prior art measures the current resulting from an applied voltage to measure the gate length and drain/source gate overlap. Examples of the prior art, using traditional IV methods are discussed in papers entitled "On the Accuracy of Channel Length Characterization of LDD MOSFET's", IEEE Transactions on Electron Devices, Vol. 33, No. 10 (October 1986), which also discusses the accuracy problems in the prior art, and "A New `Shift and Ratio` Method for MOSFET Channel-Length Extraction", IEEE Electron Device Letters, Vol. 13, No. 5 (May 1992). "An Accurate Gate Length Extraction Method for Sub-Quarter Micron MOSFET's", IEEE Transactions on Electron Devices, Vol. 43, No. 6 (June 1996), discloses a prior art method using SEM or TEM, which destroys the gate being tested and a CV method which requires a numerical simulation, which is too complicated.
Using the capacitance generated by an applied voltage as practiced by the invention will provide more accurate, simpler and nondestructive measurements of the gate length and drain/source overlap in a manufacturing environment, where a simple and inexpensive method is desired for quality control.